There is a continuing trend within the microelectronics industry to incorporate more circuitry having greater complexity on a single integrated circuit (IC) chip. Maintaining this trend generally entails shrinking the size of individual devices within the circuit by reducing the critical dimensions (CDs) of device elements along with the pitch, or the CD of such an element added to the spacing between elements. Microlithography tooling and processing techniques play an important role in resolving the features necessary to fabricate devices and, accordingly, are continually under development to meet industry milestones relating to the CD and pitch characteristics of each new technology generation.
High numerical aperture (NA) 193 nanometer (nm) optical projection stepper/scanner systems in combination with advanced photoresist processes are now capable of routinely resolving complex patterns that include isolated and dense resist features having CDs and pitches, respectively, well below the exposure wavelength. However, to meet the requirements of device design rules, which continue to push the resolution limits of existing processes and tooling, other more specialized techniques have been developed to further enhance resolution. These include multi-patterning processes in which device patterns having potentially optically unresolvable features are decomposed into two or more complementary, and more easily resolvable patterns, each containing features with larger CDs and/or a relaxed pitch.
ICs typically include a plurality of semiconductor devices formed above and/or on a semiconductor substrate and interconnect wiring. Networks of metal interconnect wiring are often used to connect the semiconductor devices. The networks of metal interconnect wiring generally include multiple layers (e.g., a metallization layers) of metal lines that are interconnected by conductive vias. The various semiconductor device layers of the IC can include, for example, the networks of metal interconnect wiring above a semiconductor substrate and can also include the semiconductor devices that are above and/or on the semiconductor substrate. The metal lines and/or semiconductor devices in adjacent semiconductor device layers are electrically connected through the interconnect vias (or interconnect contacts for example to the semiconductor devices) and various semiconductor device layers are stacked to form, for example, an interconnect structure that can include or is contacted to a front-end-of-the-line (“FEOL”) including the individual semiconductor devices (e.g., transistors, capacitors, resistors, and the like) on the semiconductor substrate and/or that can include a back-end-of-the-line (“BEOL”) interconnect structure including the networks of metal interconnect wiring above the semiconductor substrate. Within such a structure, for example, metal lines run parallel to the substrate and conductive vias and/or conduct contacts run perpendicular to the semiconductor substrate between the metal lines and/or semiconductor devices to interconnect the adjacent semiconductor device layers.
A master pattern layout for the semiconductor device layer may include, for example, target metal lines (e.g., design details for metal lines) for the semiconductor device layer and the target interconnecting via/contacts (e.g., design details for interconnecting via and/or interconnecting contacts) for interconnecting the target metal lines with an underlying semiconductor device layer (e.g., an underlying metallization layer) or an underlying semiconductor device(s). Typically, multi-patterning processes decompose the target metal lines in a semiconductor device layer into two or more complementary and more easily resolvable patterns that are transferred to corresponding photomasks and at least one additional pattern that is transferred to a separate photomask(s) for the target interconnecting via/contacts. However, cost and process efficiency are impacted by the number of photomasks required for a given multi-patterning process.
Accordingly, it is desirable to provide methods for fabricating integrated circuits using multi-patterning processes that reduce the total number of photomasks compared to conventional multi-patterning approaches. Furthermore, other desirable features and characteristics will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.